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  ? semiconductor components industries, llc, 2005 january, 2005 ? rev. 0 1 publication order number: nsb1010xv5/d NSB1010XV5T5 preferred device dual common base?collector bias resistor transistors npn and pnp silicon surface mount transistors with monolithic bias resistor network the brt (bias resistor t ransistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base ? emitter resistor. these digital transistors are designed to replace a single device and its external resistor bias network. the brt eliminates these individual components by integrating them into a single device. in the NSB1010XV5T5, two complementary brt devices are housed in the sot ? 553 package which is ideal for low power surface mount applications where board space is at a premium. ? simplifies circuit design ? reduces board space ? reduces component count ? available in 8 mm, 7 inch tape and reel ? this device is manufactured with a pb ? free external lead finish only. maximum ratings (t a = 25 c unless otherwise noted, common for q 1 and q 2 , ? minus sign for q 1 (pnp) omitted) rating symbol value unit collector-base voltage v cbo 50 vdc collector-emitter voltage v ceo 50 vdc collector current i c 100 madc thermal characteristics characteristic (one junction heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 357 (note 1) 2.9 (note 1) mw mw/ c thermal resistance junction-to-ambient r  ja 350 (note 1) c/w characteristic (both junctions heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 500 (note 1) 4.0 (note 1) mw mw/ c thermal resistance junction-to-ambient r  ja 250 (note 1) c/w junction and storage temperature t j , t stg ? 55 to +150 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. fr ? 4 @ minimum pad. ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. marking diagram preferred devices are recommended choices for future use and best overall value. 45 q1 q2 r1 r1 r2 r2 31 2 sot ? 553 case 463b us d 1 5 1 5 us = specific device code d = date code device package shipping ? ordering information NSB1010XV5T5 sot ? 553 (pb ? free) 2 mm pitch 8000/tape & reel http://onsemi.com
NSB1010XV5T5 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit q1 transistor: pnp off characteristics collector-base cutoff current (v cb = ? 50 v, i e = 0) i cbo ? ? ? 100 nadc collector-emitter cutoff current (v cb = ? 50 v, i b = 0) i ceo ? ? ? 500 nadc emitter-base cutoff current (v eb = ? 6.0 v, i c = 0) i ebo ? ? ? 1.5 madc collector-base breakdown voltage (i c = ? 10  a, i e = 0) v (br)cbo ? 50 ? ? vdc collector-emitter breakdown voltage (note 2) (i c = ? 2.0 ma, i b = 0) v (br)ceo ? 50 ? ? vdc on characteristics (note 2) collector-emitter saturation voltage (i c = ? 10 ma, i b = ? 1.0 ma) v ce(sat) ? ? ? 0.25 vdc dc current gain (v ce = ? 10 v, i c = ? 5.0 ma) h fe 15 27 ? ? output voltage (on) (v cc = ? 5.0 v, v b = ? 2.5 v, r l = 1.0 k  ) v ol ? ? ? 0.2 vdc output voltage (off) (v cc = ? 5.0 v, v b = ? 0.5 v, r l = 1.0 k  ) v oh ? 4.9 ? ? vdc input resistor r 1 3.3 4.7 6.1 k  resistor ratio r 1 /r 2 0.8 1.0 1.2 ? q2 transistor: npn off characteristics collector-base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector-emitter cutoff current (v cb = 50 v, i b = 0) i ceo ? ? 500 nadc emitter-base cutoff current (v eb = 6.0, i c = 5.0 ma) i ebo ? ? 0.5 madc on characteristics collector-base breakdown voltage (i c = 10  a, i e = 0) v (br)cbo 50 ? ? vdc collector-emitter breakdown voltage (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc dc current gain (v ce = 10 v, i c = 5.0 ma) h fe 35 60 ? collector ? emitter saturation voltage (i c = 10 ma, i b = 0.3 ma) v ce(sat) ? ? 0.25 vdc output voltage (on) (v cc = 5.0 v, v b = 2.5 v, r l = 1.0 k  ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.5 v, r l = 1.0 k  ) v oh 4.9 ? ? vdc input resistor r1 7.0 10 13 k  resistor ratio r1/r2 0.8 1.0 1.2 ? 2. pulse test: pulse width < 300  s, duty cycle < 2.0%. figure 1. derating curve 250 200 150 100 50 0 ?50 0 50 100 150 t a , ambient temperature ( c) p d , power dissipation (milliwatts) r  ja = 833 c/w
NSB1010XV5T5 http://onsemi.com 3 typical electrical characteristics ? pnp transistor 75 c 25 c ? 25 c figure 2. v ce(sat) versus i c figure 3. dc current gain figure 4. output capacitance figure 5. output current versus input voltage v in , input voltage (volts) v r , reverse bias voltage (volts) figure 6. input voltage versus output current i c , collector current (ma) i c , collector current (ma) 1 0.1 50 40 20 10 0 i c , collector current (ma) 100 10 1 100 10 1 0.001 1000 v ce(sat) , collector voltage (volts) h fe , dc current gain 6 45 50 40 30 20 10 0 0 c ob , capacitance (pf) 2 4 8 100 6 5 4 3 2 1 0 0.001 1 10 i c , collector current (ma) 10 9 8 7 10 30 20 10 0 0.1 1 40 50 v in , input voltage (volts) 75 c 25 c t a = ? 25 c 75 c 25 c t a = ? 25 c 75 c 25 c t a = ? 25 c 0.01 35 25 15 5 0.01 0.1 30 10 12 i c /i b = 10 v ce = 10 v f = 1 mhz l e = 0 v t a = 25 c v o = 5 v v o = 0.2 v
NSB1010XV5T5 http://onsemi.com 4 typical electrical characteristics ? npn transistor v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain figure 7. v ce(sat) versus i c figure 8. dc current gain figure 9. output capacitance figure 10. output current versus input voltage 1000 10 i c , collector current (ma) t a =75 c 25 c ?25 c 100 10 1 100 75 c 25 c 100 0 v in , input voltage (volts) 10 1 0.1 0.01 0.001 246810 t a =?25 c 0 i c , collector current (ma) 100 t a =?25 c 75 c 10 1 0.1 10 20 30 40 50 25 c figure 11. input voltage versus output current 0.001 v ce(sat) , maximum collector voltage (volts ) t a =?25 c 75 c 25 c 0.01 0.1 1 40 i c , collector current (ma) 0 20 50 50 0 10 203040 4 3 2 1 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) i c /i b = 10 v ce = 10 v f = 1 mhz i e = 0 ma t a = 25 c v o = 5 v v o = 0.2 v
NSB1010XV5T5 http://onsemi.com 5 package dimensions sot ? 553 5 ? lead package case 463b ? 01 issue a *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.35 0.0531 0.5 0.0197  mm inches  scale 20:1 0.5 0.0197 1.0 0.0394 0.45 0.0177 0.3 0.0118 g m 0.08 (0.003) x d 5 pl c j ? x ? ? y ? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. dim a min max min max inches 1.50 1.70 0.059 0.067 millimeters b 1.10 1.30 0.043 0.051 c 0.50 0.60 0.020 0.024 d 0.17 0.27 0.007 0.011 g 0.50 bsc 0.020 bsc j 0.08 0.18 0.003 0.007 k s a b y 12 3 4 5 s k 0.004 0.012 0.059 0.067 0.10 0.30 1.50 1.70
NSB1010XV5T5 http://onsemi.com 6 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 nsb1010xv5/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.


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